1. Field of the Invention
The present invention relates generally to memory devices and more particularly to the testing of memory devices.
1. Prior Art Description
Semiconductor memories have made significant progress in recent years. Their density, i.e. the number of bits per chip and also the number of bits per area of silicon, is ever increasing. Since the early 70s, the storage size of a memory chip has been increasing from 1024 bits to 64M bits today. 128M bits memory has also been demonstrated will be widely available very soon.
Testing these memories has become a major concern because the test time is getting longer for testing current mega- and multimega-bit memory chips. Although the subject of memory testing has been covered extensively, and a variety of test algorithms have been presented, there is no major breakthrough in improving the test time for the past 20 years. The traditional test patterns that are used for testing memory devices are listed in Table 1.
For each of all the above traditional tests, the orders of the required total test time for the memory are also summarized in the Table 1 assuming read and write cycle times of 10 ns (10.sup.-9 seconds) and a total number of N bits in the memory.
TABLE 1 ______________________________________ Total Test Time Comparison of Different Memory Test Algorithms Algorithm Order of total test time ______________________________________ Zero-One O(N) Checkerboord O(N) Walking One/Zero O(N.sup.2) Diagonal 1 #STR1## Marching Column 1 #STR2## Marching Row 1 #STR3## Complement of All Above Same as all above ______________________________________
As we can see, the Zero-one test (minimal test) patterns and the Checkerboard test (short and simple test) patterns are N type patterns. The Walking One/Zero test patterns are N.sup.2 patterns. And, the Diagonal test, the Marching Column test and the Marching Row test are NN patterns. FIG.2 shows a 1024 bit memory device having a 10 bit memory address. In general, a memory device is presented as the total bit size N or by the number of address bits. For example, a 1024 bit memory can be represented by 10 address bits. Or N=2.sup.10, or X=2.sup.5 and Y=2.sup.5. That is, N=X*Y=(2.sup.5)*(2.sup.5)=2.sup.10. There are four N type test patterns shown in FIG. 1. They are all `0`, all `2`, checker board and checker board complement respectively.
There are two basic tests for a memory device. One is a memory cell test, the other is an address decoding test. The N type patterns are used for the memory cell test. More complicated patterns are used for address decoding test. The reason for using more complicated patterns for address decoding is that the N type patterns are repetitive patterns as shown in FIG. 1. A memory device passes an N type pattern test does not mean that its decoder functions correctly. For example, in all `0` or all `1` test, the entire memory cells are filled with `0` or `1`. When we scan the entire memory cells, the output is either `0` or `1` especially for memory devices with single input bit and single output bit as shown in FIG. 2. We don know whether or not the address decoder indeed addresses every memory cell correctly because the memory device has only one output pin, which is either a `1` or a `0`. There is not enough information to determine which memory cell is addressed by the decoder. Therefore, these tests are based on the assumption that the address decoder functions correctly, and more sophisticated patterns were developed to test and ensure the proper function of the decoder.
The first pattern that was developed to test the address decoder is the `Walking` pattern as shown in FIG. 3. FIG. 3 shows walking a `1` through a fields of `0`. The complement of `Walking One` pattern is a `Walking Zero`, which is walking a `0` through a field of `1`. As shown in FIG. 3a, the entire memory cells are filled with `0` except location 0. A `1` is written into location 0. Then memory read operations of the entire memory cells are performed. Only at location 0, a `1` is read and a `0` is read from each of all other locations. To prove the address decoder decodes location 0 correctly, it is required to read the memory cell N times. After having proven that location 0 decodes correctly, location 0 is changed to a `0` and location 1 is changed to a `1` as shown in FIG. 3b. Then read operations of the entire memory are performed. This time only location 1 should have a `1` and each of all other locations should have a `0`. To test 2 locations, it requires 2*N read operations. In order to test the decoder completely, a `1` has to walk from location 0 to location N. Therefore it requires N*N times. This kind of patterns are referred to as N square (N.sup.2) patterns.
As the size of memory keeps on increasing, testing with N.sup.2 patterns are too time consuming. In most cases, it would exceed 1 hour. In order to reduce the test time, the N.sqroot.N patterns were developed. FIGS. 4 , 5 and 6 illustrate the N.sqroot.N patterns. FIG. 4 is a sliding diagonal pattern. FIG. 5 is a marching column pattern and FIG. 6 is a marching row pattern. Even with the N.sqroot.N patterns , the test time is longer than 1 hour for most of the large size memory devices.
Moreover, these traditional schemes have significant restrictions, such as Zero-One and Checkerboard tests have a very questionable fault coverage, and for correct application of checkerboard and sliding diagonal, the exact location of each memory cell must be known. That means that if the address lines are scrambled within the chip, which is often the case, the scramble table must be known in order to be able to perform the tests.
As summarized above, to test memory using conventional tests (such as Zero-One test and checkerboard test), it is necessary that the address decoder functions correctly. And, to test address decoder, even with the N.sqroot.N pattern test (such as the marching column test, the marching row test and the sliding diagonal test), it is time-consuming for most of the large size memory . In addition, it may require that the memory technology be known (i.e. whether the memory device returns an AND function or an OR function when multiple cells are read).